HDL 4.5倍分頻

ID:105323 · 發表于 2016-2-23 01:15

Verilog實現的4.5倍分頻
代碼如下：

module div_4_5(clk,rst,clkout);
input clk,rst;
output clkout;

reg [3:0] cnt_p;
reg [3:0] cnt_n;

reg clk_p,clk_n;

assign clkout=clk_p || clk_n;

always @ (posedge clk or negedge rst)
begin
if(!rst)
  cnt_p<=4'd0;
else if(cnt_p==4'd8)
  cnt_p<=4'd0;
else
  cnt_p<=cnt_p+4'd1;
end

always @ (posedge clk or negedge rst)
begin
if(!rst)
  clk_p<=1'd0;
else if(cnt_p==4'd1 || cnt_p==4'd2 || cnt_p==4'd6 || cnt_p==4'd7)
  clk_p<=1'd1;
else
  clk_p<=1'd0;
end

always @ (negedge clk or negedge rst)
begin
if(!rst)
  cnt_n<=4'd0;
else if(cnt_p==3'd1)
  cnt_n<=4'd1;
else if(cnt_n==4'd8)
  cnt_n<=4'd0;
else if(cnt_n==4'd0)
  cnt_n<=4'd0;
else
  cnt_n<=cnt_n+4'd1;
end

always @ (negedge clk or negedge rst)
begin
if(!rst)
  clk_n<=1'd0;
else if(cnt_n==4'd1 || cnt_n==4'd2 || cnt_n==4'd6 || cnt_n==4'd5)
  clk_n<=1'd1;
else
  clk_n<=1'd0;
end

endmodule

仿真結果：

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HDL 4.5倍分頻